The week's pick
Reseach Article
DFM Challenges and Solutions for 14nm FinFET
| Communications on Applied Electronics |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 2 - Number 3 |
| Year of Publication: 2015 |
| Authors: Ravi Dhanani, Bhavesh Soni |
10.5120/cae-1693
|
Ravi Dhanani, Bhavesh Soni . DFM Challenges and Solutions for 14nm FinFET. Communications on Applied Electronics. 2, 3 ( June 2015), 33-36. DOI=10.5120/cae-1693
Abstract
In this Paper, advanced methods for DFM Verification and solutions are presented for lower nodes. It includes the need for Litho-Friendly Design, CMP aware Fill, Process Variation Issues and its impact on the design. Along with the DRC/LVS checks which deal with the physical verification processes, in lower technologies nodes, DFM should also be equally given importance as without it, it is impossible to achieve the silicon with maximum yield. Goal of DFM is to improve yield by minimizing defects like systematic, random and parametric defects through prevention, detection and fixing the hotspots.
References
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- Ahmad Abdulghany, Rami Fathy, Luigi Capodieci, Piyush Pathak, Sriram Madhuvan, Shobhit Malik, "Smart Double-Cut Via Insertion Flow with Dynamic Design Rules Compliance for Fast New Technology Adoption", unpublished.
- Robert Boone, Domenico Loparco, Fabio Melchiori, Matt Thompson, "Critical Feature and Improvability Analysis: An Effective Path to DFM Closure", unpublished.
- Mentor Graphics Calire Design for Manufacturing related datasheets.
- KK Lin, Jeff Wilson, and Joe Kwan, "DFM Solutions for 14nm: Samsung and Mentor Graphics", On Demand Webinar, Decemeber 2014.
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