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Optimizing Current Characteristics of 32 nm FinFET by Controlling Fin Width
| Communications on Applied Electronics |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 2 - Number 7 |
| Year of Publication: 2015 |
| Authors: Neha Somra, Kanika Mishra, Ravinder Singh Sawhney |
10.5120/cae2015651795
|
Neha Somra, Kanika Mishra, Ravinder Singh Sawhney . Optimizing Current Characteristics of 32 nm FinFET by Controlling Fin Width. Communications on Applied Electronics. 2, 7 ( August 2015), 1-5. DOI=10.5120/cae2015651795
Abstract
The FinFET transistor structure assures to rejuvenate the chip industry by rescuing it from the short-channel effects that limits the device scalability endured by current planar transistor structures. In this thesis, we report the design, fabrication and physical characteristics of n-channel FinFET with physical gate length of 32nm using visual TCAD (steady state analysis). All the measurements were performed at a supply voltage of 1.5V and 5 nm oxide thickness. We report the drain saturation current is 0.0343453mA at Vg=1V and 0.0410523mA at Vg=1.5V which indicates approximately 20 percent hike in Id with increase in 0.5V gate voltage. We simulate the device for distinct fin thickness from 5 nm to 50 nm. In this thesis we report, for 32 nm gate length FinFET having above 21.33 nm fin width would consequence in short channel effects in spite of having high drain current.
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