The week's pick
Reseach Article
Simulation of n-FinFET Performance Reliance on Varying Combinations of Gate Material and Oxide
| Communications on Applied Electronics |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 2 - Number 7 |
| Year of Publication: 2015 |
| Authors: Kanika Mishra, Neha Somra, Ravinder Singh Sawhney |
10.5120/cae2015651798
|
Kanika Mishra, Neha Somra, Ravinder Singh Sawhney . Simulation of n-FinFET Performance Reliance on Varying Combinations of Gate Material and Oxide. Communications on Applied Electronics. 2, 7 ( August 2015), 12-16. DOI=10.5120/cae2015651798
Abstract
In this paper an n-type double gate FinFET at a gate length of 22nm is reported. Here the device performance of FinFET under different gate materials and also under different buried oxides is construed. Firstly, the drain current under different gate materials, with different work functions and SiO2 being the buried oxide has been obtained. A transfer characteristic curve has then been obtained comparing the drain current for different gate materials at a given supply voltage of 0.5 V. Secondly, the transfer characteristic curve, comparing the drain currents obtained under different buried oxides at 0.5 V supply voltage with Aluminium being the gate has been obtained. And lastly obtained is the device performance for different combinations of gate materials and buried oxides and the results were compared. It can be inferred that, a metal gate and a high k dielectric is what gives a good performance at nanometre ranges. All the simulations have been done in Visual TCAD.
References
- Bin Yu, Leland Chang, Shibly Ahmed, Haihong Wang, Scott Bell, Chih-Yuh Yang, Cyrus Tabery, Chau Ho, Qi Xiang, Tsu-Jae King, Jeffrey Bokor, Chenming Hu, Ming-Ren Lin, and David Kyser “FinFET Scaling to 10nm Gate Length”, International Electronic Devices Meeting, pp 251-254, December 8-11, 2002.
- P. M. Solomon, K. W. Guarini, Y. Zhang et al., “Two gates are better than one,” IEEE Circuits and Devices Magazine, vol. 19, no. 1, pp. 48–62, 2003.
- V. Subramanian, A. Mercha, B. Parvais, J. Loo, C. Gustin, M. Dehan, N. Collaert, M. Jurczak, G. Groeseneken 1, W. Sansen 1, S. Decoutere “Impact of fin width on digital and analog performances of n-FinFETs”, IMEC, Kapeldreef 75, 3001 Leuven, Belgium, Solid State Electronics, pp 551-559, 2007.
- LexInnova, “FinFET: Extending Moore’s Law” pp. 3-6.
- Scott E. Thompson and Srivatsan Parthasarathy “Moore’s law: the future of Si microelectronics”, SWAMP Center, Department of Electrical and Computer Engineering, University of Florida, Gainsville, FL 32611-6130 USA.
- Gordon E. Moore “Cramming more components onto integrated circuits”, Director, Research and Development Laboratories, Fairchild Semiconductor division of Fairchild Camera and Instrument Corp, Electronics, Vol. 38, No. 8, April 19, 1965.
- Chau, R.; Datta, S.; Doczy, M.; Doyle, B.; Kavalieros J.; & Metz M. (2004). High-k/Metal– Gate Stack and Its MOSFET Characteristics, IEEE Electron Device Lett., vol. 25, pp. 408-410.
- T. Rudenko, N. Collaert, S. De Gendt, V. Kilchytska, M. Jurczak, D. Flandre, “Effective mobility in FinFET structures with HfO2 and SiON gate dielectrics and TaN gate electrode”, Microelectronic Engineering 80, pp 386-389, 2005.
- Daewon Ha, H. Takeuchi, Y.-K. Choi, T.-J. King, W.P. Bai, D.-L. Kwong, A. Aganval, and M. Ameen “Molybdenum-Gate HfO2 CMOS FinFET Technology”, IEEE International Electronic Devices Meeting, pp 643-646, December 13-15, 2004.
- Digh Hisamoto, Member, IEEE, Wen-Chin Lee, Jakub Kedzierski, Hideki Takeuchi, Kazuya Asano, Member, IEEE, Charles Kuo, Erik Anderson, Tsu-Jae King, Jeffrey Bokor, Fellow, IEEE, and Chenming Hu, Fellow, IEEE “FinFET—A Self-Aligned Double-Gate MOSFET Scalable to 20 nm”, IEEE Transactions on Electron Devices, Vol. 47, No. 12, December 2000.
- S. L. Tripathi and R.A. Mishra “Performance Improvement of FinFET Using Spacer With High K Dielectric”, Department of Electronics and Communication Engineering, MNNIT, Allahabad, India, Journal of Electronic Devices, Vol. 17, pp 1447-1451, 2013.
- Flavia Princess Nesamani, Geethanjali Raveendran, Dr.V. Lakshmi Prabha “Performance Improvement of FinFET using Nitride Spacer”, International Journal of Engineering Trends and Technology, Vol. 4, Issue 3, 2013.
- A. P. Huang, Z. C. Yang and Paul K. Chu (2010). Hafnium-based High-k Gate Dielectrics, Advances in Solid State Circuit Technologies, Paul K Chu (Ed.), ISBN: 978-953-307-086-5, InTech, DOI: 10.5772/8631. Available from: http://www.intechopen.com/books/ advances-in-solid-state-circuit-technologies/hafnium-based-high-k-gate-dielectrics.
- R. Collin Johnson “III-V FinFET Fabbed on Silicon”, July 2013.
- Mittal, S. Gupta, A. Nainani, M.C. Abraham, K. Schuegraf, S. Lodha, U. Ganguly “Epi Defined (ED) FinFET: An alternate device architecture for high mobility Ge channel integration in PMOSFET”.
Index Terms
Keywords