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Modified PFAL Adiabatic Technique for Low Power

by Bhakti Patel, Poonam Kadam
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Communications on Applied Electronics
Foundation of Computer Science (FCS), NY, USA
Volume 3 - Number 7
Year of Publication: 2015
Authors: Bhakti Patel, Poonam Kadam
10.5120/cae2015652000

Bhakti Patel, Poonam Kadam . Modified PFAL Adiabatic Technique for Low Power. Communications on Applied Electronics. 3, 7 ( December 2015), 40-43. DOI=10.5120/cae2015652000

@article{ 10.5120/cae2015652000,
author = { Bhakti Patel, Poonam Kadam },
title = { Modified PFAL Adiabatic Technique for Low Power },
journal = { Communications on Applied Electronics },
issue_date = { December 2015 },
volume = { 3 },
number = { 7 },
month = { December },
year = { 2015 },
issn = { 2394-4714 },
pages = { 40-43 },
numpages = {9},
url = { https://www.caeaccess.org/archives/volume3/number7/482-2015652000/ },
doi = { 10.5120/cae2015652000 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2023-09-04T19:44:08.368464+05:30
%A Bhakti Patel
%A Poonam Kadam
%T Modified PFAL Adiabatic Technique for Low Power
%J Communications on Applied Electronics
%@ 2394-4714
%V 3
%N 7
%P 40-43
%D 2015
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper presents the quasi-adiabatic Modified Positive Feedback Adiabatic Logic (MPFAL) for low power operation through energy recovery technique. The circuit of positive feedback adiabatic (PFAL) inverter has been improved here. It is a diode-free and dual rail logic offering both the true and complementary outputs. Validation is done through basic digital gate circuits. Comparison with static CMOS and PFAL circuits are made to prove the designs. In post-layout simulations, energy savings of 27% is achieved against the optimized PFAL Inverter, NAND and NOR gate circuits. The various improvement results are analyzed in LTSPICE tool.

References
  1. Arun Kumar, Manoj Sharma, Design and analysis of MUX using adiabatic techniques ECRL and PFAL, IEEE , 2013.
  2. G. Sujatha, Dilli kumar, “design of 2x2 bit cube in different low power Techniques for portable devices”, International Journal of Advances in Science Engineering and Technology, ISSN: 2321-900, Volume- 1, Issue- 2, Oct-2013.
  3. LTspice/SwitcherCAD III, Version 2.24i, US Pacific.
  4. A. Vetuli, S. Di Pascoli, and L.M. Reyneri, “Positive feedback in adiabatic logic”, Electron.Lett, Vol.32, Sept. 1996.
  5. A. Blotti, S. Di Pascoli and R, Saletti, Sim le model for positive-feedback estimation adiabatic logic, Electronics letters, 20th January 2000, Vol. 36 No. 2.
  6. Bhakti Patel, Poonam Kadam, “Comparative Analysis of Adiabatic Logic Techniques”,IJCA,Sept.2015
  7. Manoj Sharma and Arti Noor,” Reconfigurable CPLAG and Modified PFAL Adiabatic Logic Circuits”, Advanced Electronics, Vol.2015
  8. Ashmeet Kaur Bakshi, Manoj Sharma, Design of Basic Gates using ECRL and PFAL, IEEE, 2013.
  9. B. Dilli Kumar, M. Bharathi, Design of Energy Efficient Arithmetic Circuits Using Charge Recovery Adiabatic Logic, International Journal of Engineering Trends and Technology- Volume 4, Issue1- 2013.
  10. Renuka Verma, Rajesh Mehra, Area Efficient Layout Design Analysis of CMOS Barrrel Shifter, EATHD-2015 Conference Proceeding, 14-15 March, 2015.
Index Terms

Computer Science
Information Sciences

Keywords

Static CMOS PFAL NAND NOR

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