Systolic array computation can be done by the arrangement of multi processors in an array which enables the data to follows synchronously across the array and between neighbor processor which speeded up the computation comparing with single processor computation. A sinusoidal sequence is generated in a considerably shorter time by using a fully pipelined systolic array. FPGA (Field Programmable Gate Array) is selected as a VLSI (Very Large Scale Integration) platform device since, FPGA can provide a certain computations at very high frequencies with systolic computing. The present work is concentrated on developing hardware model for systolic array implementation for sinusoidal sequence generator using VHDL (Very High Speed Integrated Circuits Hardware Description Language) as a platform. The design is implemented using simulator and synthesized on Cyclone III FPGA board.

Systolic Array FPGA VLSI VHDL Altera