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Analysis of Array Multiplier and Vedic Multiplier using Xilinx
| Communications on Applied Electronics |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 5 - Number 1 |
| Year of Publication: 2016 |
| Authors: Kaustubh Manikrao Gaikwad, Mahesh Shrikant Chavan |
10.5120/cae2016652140
|
Kaustubh Manikrao Gaikwad, Mahesh Shrikant Chavan . Analysis of Array Multiplier and Vedic Multiplier using Xilinx. Communications on Applied Electronics. 5, 1 ( May 2016), 13-16. DOI=10.5120/cae2016652140
Abstract
Many important signal processing systems are designed on VLSI platform as the integration growing rapidly. The signal processing systems and applications requires large computation capacity and hence takes considerable amount of energy. In the VLSI system design performance and area are the two very important parameters. Generally performance of any system is determined by the performance of the element that is multiplier. Multiplier is the slow element in the system. The two terms the area and speed are the main hurdles before the researcher because to improve the speed results in large area. As a result, while designing of multiplier with optimised speed and area is the major challenge. Therefore design of low-power multiplier has been an important area in VLSI system design research. Many researchers have been worked at circuit and logic, technology, physical level on designing low power, low area multipliers. The present paper deals with design and implementation of efficient high speed 16x16 multiplier using various algorithms like array & booth, and using Vedic operators. Multipliers are compared on the basis of optimized area, speed and memory required.
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