The week's pick
Reseach Article
Reversible Logic Synthesis of Modulo Operation using an Optimized Parallel Binary Adder/Subtractor
| Communications on Applied Electronics |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 5 - Number 10 |
| Year of Publication: 2016 |
| Authors: Shaunak Basu, Subhashree Basu |
10.5120/cae2016652385
|
Shaunak Basu, Subhashree Basu . Reversible Logic Synthesis of Modulo Operation using an Optimized Parallel Binary Adder/Subtractor. Communications on Applied Electronics. 5, 10 ( Sep 2016), 23-28. DOI=10.5120/cae2016652385
Abstract
Reversible logic is gaining importance in recent years largely due to its property of low power consumption. It has a wide range of applications which include advance computing, low power CMOS, optical information processing, quantum computing, DNA cryptography and nanotechnology. Reversible gates are the building blocks of quantum computation. This paper presents an optimized parallel binary adder/subtractor using existing reversible gates which is further used to implement a novel circuit capable of performing modulo operation. All circuits have been modeled and verified using Verilog and Modelsim. An overall analysis of the modulo circuit and a comparative study of the proposed parallel adder/subtractor with respect to previous designs in terms of the number of gates, number of garbage outputs and quantum costs is presented.
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