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Design of parallelized HDWT Hardware Architecture with an Increased Throughput

James Ntaganda. Published in Parallel Computing.

Communications on Applied Electronics
Year of Publication: 2016
Publisher: Foundation of Computer Science (FCS), NY, USA
Authors: James Ntaganda
10.5120/cae2016652225

James Ntaganda. Design of parallelized HDWT Hardware Architecture with an Increased Throughput. Communications on Applied Electronics 5(2):22-27, May 2016. BibTeX

@article{10.5120/cae2016652225,
	author = {James Ntaganda},
	title = {Design of parallelized HDWT Hardware Architecture with an Increased Throughput},
	journal = {Communications on Applied Electronics},
	issue_date = {May 2016},
	volume = {5},
	number = {2},
	month = {May},
	year = {2016},
	issn = {2394-4714},
	pages = {22-27},
	numpages = {6},
	url = {http://www.caeaccess.org/archives/volume5/number2/598-2016652225},
	doi = {10.5120/cae2016652225},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}
}

Abstract

Discrete Wavelet Transform-based applications such as Multimedia CODECs require intensive computation. With modern technologies, Hardware-Software Co-designing has become a common practice. Such designs are regarded as SoC (System on Chip), where designers dedicate hardware modules for computational-intensive functions and are called routinely by the main program code, which is why they are called hardware accelerators. Comparatively, multiplication operation takes longer, consumes more processing power and utilizes more hardware resources. Keeping other factors constant, any technique that can reduce multiplication operations is considered a better approach in hardware designs. This paper is based on our previous published concept, where we exploited the simplicity of Haar function and proposed a recursive structure of a non normalized Haar Discreet Transform. We implemented it as a multiplier-less Haar DWT (HDWT) hardware module which can spatially transform 16x16 arrays. However, in our previous work, most of the processing nodes remained idle and exhibited less throughput. To increase parallelization and hence throughput, in this paper we propose “mirror-reflection” approach. This reduces the number of redundant and idle processing nodes in the circuit module and makes the circuitry scalable. With this approach, circuit redundancy was reduced and circuit utilization efficiency increased from 47% to 69%. The scalable hardware Module is implemented using FPGA.

References

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Keywords

Haar DWT, Image Compression, Hardware Implementation, Mirror-reflection, FPGA