CFP last date
01 May 2024
Reseach Article

Insights of Performance Enhancement Techniques on FinFET-based SRAM Cells

by Girish H., Shashikumar D. R.
Communications on Applied Electronics
Foundation of Computer Science (FCS), NY, USA
Volume 5 - Number 6
Year of Publication: 2016
Authors: Girish H., Shashikumar D. R.
10.5120/cae2016652312

Girish H., Shashikumar D. R. . Insights of Performance Enhancement Techniques on FinFET-based SRAM Cells. Communications on Applied Electronics. 5, 6 ( Jul 2016), 20-26. DOI=10.5120/cae2016652312

@article{ 10.5120/cae2016652312,
author = { Girish H., Shashikumar D. R. },
title = { Insights of Performance Enhancement Techniques on FinFET-based SRAM Cells },
journal = { Communications on Applied Electronics },
issue_date = { Jul 2016 },
volume = { 5 },
number = { 6 },
month = { Jul },
year = { 2016 },
issn = { 2394-4714 },
pages = { 20-26 },
numpages = {9},
url = { https://www.caeaccess.org/archives/volume5/number6/626-2016652312/ },
doi = { 10.5120/cae2016652312 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2023-09-04T19:55:34.669561+05:30
%A Girish H.
%A Shashikumar D. R.
%T Insights of Performance Enhancement Techniques on FinFET-based SRAM Cells
%J Communications on Applied Electronics
%@ 2394-4714
%V 5
%N 6
%P 20-26
%D 2016
%I Foundation of Computer Science (FCS), NY, USA
Abstract

With the advancement in the energy efficient storage system, FinFET has already gained a pace in the area of computational memory management. However, after reviewing the research work focusing on FinFET based SRAM cells till date, we found that amount of research work towards enhancement of the design principle has not been much in number. Hence, we study some of the recently introduced research contribution towards enhancing the design performance of FinFET based SRAM cells and found that majority of the technique have both advantages and limitations too. We also highlights the significant research gap from the existing studies in order to assist the readers aware of the practicality of the research progress in this regards.

References
  1. Chen, Emerging Nanoelectronic Devices, John Wiley & Sons, 2015
  2. R. Reis, Y. Cao, G. Wirth, Circuit Design for Reliability, Springer, 08-Nov-2014
  3. N. Kaushik, B.K. Kaushik, D. Kaur, M.K. Majumder, “Independent Gate SRAM based on Asymmetric gate to Source / Drain Overlap-Underlap Device FinFET”, Springer- Progress in VLSI Design and Test: 16th International Symposium on VSLI Design and Test, 2012
  4. W. Han, Z. M. Wang, ‘Toward Quantum FinFET’, Springer Science & Business Media, 2013
  5. C. Shin, ‘Variation-Aware Advanced CMOS Devices and SRAM’, Springer, 2016
  6. B. Prince, ‘Vertical 3D Memory Technologies’, John Wiley & Sons, Aug-2014
  7. K. Ishibashi, K. Osada, ‘Low Power and Reliable SRAM Memory Cell and Array Design’, Springer Science & Business Media, 2011
  8. G. Nicolescu, I. O'Connor, C. Piguet, ‘Design Technology for Heterogeneous Embedded Systems’, Springer Science & Business Media, 2012
  9. D. Chattopadhyay, Electronics (fundamentals And Applications), New Age International, 2006
  10. http://www.synopsys.com/Tools/Implementation/SignOff/Pages/StarRC-ds.aspx
  11. http://www.ti.com/tool/tina-ti
  12. http://www.synopsys.com/tools/tcad/Pages/default.aspx
  13. https://www.mentor.com/products/ic_nanometer_design/verification-signoff/physical-verification/
  14. M. Bayoumi, A. Dutta, “FinFET based SRAM Design: A Survey on Device, Circuit, and Technology Issues”, IEEE International Conference on Electronics, Circuits and Systems, pp/387-390, 2014
  15. M.Parimaladevia, D.Sharmilab, L.Kowsikaa, “A Survey on the Performance Analysis of 6t Sram Cell Using Novel Devices”, South Asian Journal of Engineering and Technology, Vol.2, No.18, pp.71–77, 2016
  16. D. Bhattacharya and N. K. Jha, “FinFETs: From Devices to Architectures”, Hindawi Publishing Corporation, Advances in Electronics, 2014
  17. D. Burnett, S. Parihar, H. Ramamurthy, S. Balasubramanian, “FinFET SRAM Design Challenges”, IEEE International Conference on IC Design and Technologies, pp.1-4, 2014
  18. X. Zhang, D. Connelly, P. Zheng, H. Takeuchi, “Analysis of 7/8-nm Bulk-Si FinFET Technologies for 6T-SRAM Scaling”, IEEE Transactions On Electron Devices, vol. 63, no. 4, april 2016
  19. X. Zhang, “Simulation-based Study of Super-steep Retrograde Doped Bulk FinFET Technology and 6T-SRAM Yield”, Doctorial Thesis on University of California at Berkeley, 2016
  20. J.H. Lee, “FinFETs: Design at 14 nm Node and Key Characteristics”, Springer Journal of Nano Devices and Circuit Techniques for Low-Energy Applications and Energy Harvesting, 2016
  21. T. Song, W. Rim, S. Park, Y. Kim, “A 10nm FinFET 128Mb SRAM with Assist Adjustment System for Power, Performance, and Area Optimization”, IEEE International Solid-State Circuits Conference, 2016
  22. M. Ansari, H. A. Kusha, B. Ebrahimi, Z. Navabi, “A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20 nm FinFET technologies”, Elsevier Journal of INTEGRATION, the VLSI journal, vol.50, pp.91–106, 2015
  23. L. M. Dani, G. Singh, M. Kaur, “FinFET based 6T SRAM Cell for Nanoscaled Technologies”, International Journal of Computer Applications, Vol.127, No.13, October 2015
  24. S. K. Gupta and K. Roy, “Low Power Robust FinFET-Based SRAM Design in Scaled Technologies”, Springer Journal of Circuit Design for Reliability, 2015
  25. R. S. Kushwah and S. Akashe, “FinFET-based 6T SRAM cell design: analysis of performance metric, process variation and temperature effect”, InderScience International Journal of Signal and Imaging Systems Engineering, Vol. 8, No. 6, 2015
  26. J. Park, Y. Yang, H. Jeong, S. C. Song, J. Wang, “Design of a 22-nm FinFET-Based SRAM With Read Buffer for Near-Threshold Voltage Operation”, IEEE Transactions On Electron Devices, vol. 62, no. 6, June 2015
  27. I. Manju, A. S. Kumar, “A 22 nm FinFET based 6T-SRAM cell design with scaled supply voltage for increased read access time”, Springer Analog Integration Circular of Signal Process, 2015
  28. H. Farkhani, A. Peiravi, F. Moradi, “A new write assist technique for SRAM design in 65 nm CMOS technology”, Elsevier- Integration, the VLSI journal, vol.50, pp.16–27, 2015
  29. A. Shafaei, S. Chen, Y.Wang and M. Pedram, “A Cross-Layer Framework for Designing and Optimizing Deeply-Scaled FinFET-Based Cache Memories”, Journal of Low Power Electronics and Applications, vol.5, pp.165-182, 2015
  30. B. Zeinali, J. K. Madsen, P. Raghavan, F. Moradi, “Sub-threshold SRAM Design in 14 nm FinFET Technology with Improved Access Time and Leakage Power”, IEEE Computer Society Annual Symposium on VLSI, 2015
  31. P. K. Pal, B. K. Kaushik, S. Dasgupta, “Design Metrics Improvement for SRAMs Using Symmetric Dual-k Spacer (SymD-k) FinFETs”, IEEE Transactions On Electron Devices, vol. 61, no. 4, April 2014
  32. D. Ghai, S. P. Mohanty, and G. Thakral, “Comparative Analysis of Double Gate FinFET Configurations for Analog Circuit Design”, IEEE International Midwest Symposium on Circuits and Systems, pp.809-812, 2013
  33. P. Kerber, R. Kanj, and R. V. Joshi, “Strained SOI FINFET SRAM Design”, IEEE Electron Device Letters, vol. 34, no. 7, July 2013
  34. H. Villacorta, V. Champac, S. Bota, J. Segura, “FinFET SRAM hardening through design and technology parameters considering process variations”, IEEE European Conference on radiation and Its Effects on Components and Systems, pp.1-7, 2013
  35. Wang, Modeling leakage power reduction in VLSI as optimization problems, Springer, 2007
  36. Lu, Layout Optimization in VLSI Design, 2001
  37. Kashfi, Multi-objective optimization techniques for VLSI circuits, 2011
Index Terms

Computer Science
Information Sciences

Keywords

FinFET SRAM Leakage Power Energy Efficiency CMOS MOSFET