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Simplification of Ternary Function using Variable Entered Mapping Technique

Prashant S. Wankhade, Gajanan Sarate. Published in Information Sciences.

Communications on Applied Electronics
Year of Publication: 2016
Publisher: Foundation of Computer Science (FCS), NY, USA
Authors: Prashant S. Wankhade, Gajanan Sarate
10.5120/cae2016652377

Prashant S Wankhade and Gajanan Sarate. Simplification of Ternary Function using Variable Entered Mapping Technique. Communications on Applied Electronics 5(9):44-50, September 2016. BibTeX

@article{10.5120/cae2016652377,
	author = {Prashant S. Wankhade and Gajanan Sarate},
	title = {Simplification of Ternary Function using Variable Entered Mapping Technique},
	journal = {Communications on Applied Electronics},
	issue_date = {September 2016},
	volume = {5},
	number = {9},
	month = {Sep},
	year = {2016},
	issn = {2394-4714},
	pages = {44-50},
	numpages = {7},
	url = {http://www.caeaccess.org/archives/volume5/number9/652-2016652377},
	doi = {10.5120/cae2016652377},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}
}

Abstract

This paper describes the steps for minimization of ternary function i.e. three level logic using variable entered mapping technique. Here we applied VEM technique successfully to the ternary function and result is verified using truth table of given ternary equations. We also implemented simplified expression using decoder and ternary gates as well as using ternary multiplexer.

It will be more difficult as radix of the number system increases to get more difficult in minimization and to design circuit.

In this paper we successfully applied VEM technique to ternary system, the proposed technique is developed for the ternary logic function simplification. It incorporates all designed rules for ternary logic system design and gives the output in the form of Sum-of-Product (SOP) terms.

Generally VEM technique is used for the minimization of binary function so the rule used here are different than binary logic. Output equation of ternary digital system is in the form of F = F2 + 1. (F1) Where, F2 = 2’s minterms and F1 = 1’s minterms.

References

  1. Porat DI. Three-valued Digital Systems. Proc. IEEE. 1969; 116: 947-954.
  2. Marek Perkowski (2006): Introduction to multivalued logic Available as: http://web.cecs.pdx.edu/~mperkows temp/JULY/2006.Introduction-to-MV-logic.ppt
  3. S.L.Hurst. (1984): Multivalued logic - Its status and its future, IEEE Trans .on Computers, vol. C-33, pp. 1160-1179..
  4. E. Sipos. et. al. (2008): A Method to Design Ternary Multiplexers Controlled by Ternary Signals Based on SUS-LOC,Proceedings of the IEEE International Conference on Automation, quality and Testing, Robotics, IEEE Computer Society, Vol.3,pp.402-407..
  5. Sheng Lin et al. (2009): CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits, IEEE Trans. On Nanotechnology, Vol. PP, Issue.99, pp.1-1.
  6. K. C. Smith. (1981): The Prospects for Multivalued Logic: A Technology and Applications View, IEEE Transactions on Computers, Vol. C-30, Issue.9, pp.619-634...
  7. S.L.Hurst. (1984): Multivalued logic - Its status and its future, IEEE Trans .on Computers, vol. C-33, pp. 1160-1179.
  8. A.P. Dhande et. al. (2005): Design And Implementation Of 2 Bit Ternary ALU Slice, 3rd International Conference, Sciences of Electronic (SETIT), IEEE Transc., pp.1-11.
  9. Jorge Pedraza Arpasi (2003): A Brief Introduction to Ternary Logic, pp.1-13.
  10. Raymond E.Miller. (1966): Switching Theory, Vol. I, John Wiley & Sons, pp.8-9
  11. D. I. Porat. (1969): Three-valued digital systems, PROC. IEEE, Vol. 116, No. 6, pp.947-954.
  12. D. Venkat Reddy et. al (2008): Sequential Circuits In The Framework Of (2n+1)-ary Discrete Logic, IJCSNS International Journal of Computer Science and Network Security, Vol.8 No.7, July, pp.175-181..
  13. Jorge Pedraza Arpasi (2003): A Brief Introduction to Ternary Logic, pp.1-13.
  14. Chung-Yu-Wu. Design& application of pipelined dynamic CMOS ternary logic & simple ternary dfferential logic”IEEE journal on solid state circuits. 1993; 28: 895-906.
  15. K.C. Smith. (1988): Multiple-Valued Logic, A Tutorial and Appreciation, Survey & Tutorial Series, IEEE Transc. In computers,Vol.21, Issue.4, pp.17-27
  16. Robert L.Herrmann. (1968): Selection and implementation of a ternary switching algebra, Proceedings of AFIPS Joint Computer Conference, Spring Joint Computer Conference, pp.283-290.
  17. E. Sipos. et. al. (2008): A Method to Design Ternary Multiplexers Controlled by Ternary Signals Based on SUS-LOC,Proceedings of the IEEE International Conference on Automation, quality and Testing, Robotics, IEEE Computer Society, Vol.3,pp.402-407.
  18. M. Yoeli, et al., “Logical Design of Ternary Switching Circuits”, IEEE Transactions on Electronic Computers 1965.
  19. H.T.Moufftah, “Study on Implementation of Three Valued Logic”, Proc.ISMVL, pp.359-372, May 1995.
  20. [ Alexander E. et al., “Comparative Analysis of Algorithms For The Minimization Of Multivalued Logic Functions” CH2766 - 4/89/0000 – 0559 IEEE, pp.559-564, 1989.
  21. T.N. Rajashekhara, I-Shi Eric Chen, “Fast Adder Design Using Redundant Sign Digit Number”, International Journal of Electronics, 1990
  22. P s wankhade,Dr Gajanan sarate “Optimization of ternary combinational system” IJSER,vol 6,issue5,may2015.
  23. P s wankhade,Dr Gajanan sarate “Minimisation of Multile value function using quine mac clusky technique” IJCA,vol 143-No 07,june2016.

Keywords

Multivalued logic,(MVL) Radix; Sum-of-Product (SOP); Ternary;,T-gate MEV, Unary function.