CFP last date
01 January 2025
Call for Paper
February Edition
CAE solicits high quality original research papers for the upcoming February edition of the journal. The last date of research paper submission is 01 January 2025

Submit your paper
Know more
The week's pick
Responsive image
Property (Land) Registration Management Using Blockchain in Nigeria

A. Festus Osuolale Ojebiyi David-Daniel Seriki Oluwasogo
Random Articles
Reseach Article

Elliptic Filter Implementation using Xilinx system Generator for Processing of ECG Signal

by Kaustubh M. Gaikwad, Mahesh Chavan
journal cover thumbnail

Communications on Applied Electronics
Foundation of Computer Science (FCS), NY, USA
Volume 7 - Number 12
Year of Publication: 2018
Authors: Kaustubh M. Gaikwad, Mahesh Chavan
10.5120/cae2018652743

Kaustubh M. Gaikwad, Mahesh Chavan . Elliptic Filter Implementation using Xilinx system Generator for Processing of ECG Signal. Communications on Applied Electronics. 7, 12 ( Jan 2018), 25-29. DOI=10.5120/cae2018652743

@article{ 10.5120/cae2018652743,
author = { Kaustubh M. Gaikwad, Mahesh Chavan },
title = { Elliptic Filter Implementation using Xilinx system Generator for Processing of ECG Signal },
journal = { Communications on Applied Electronics },
issue_date = { Jan 2018 },
volume = { 7 },
number = { 12 },
month = { Jan },
year = { 2018 },
issn = { 2394-4714 },
pages = { 25-29 },
numpages = {9},
url = { https://www.caeaccess.org/archives/volume7/number12/796-2018652743/ },
doi = { 10.5120/cae2018652743 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2023-09-04T20:03:29.853211+05:30
%A Kaustubh M. Gaikwad
%A Mahesh Chavan
%T Elliptic Filter Implementation using Xilinx system Generator for Processing of ECG Signal
%J Communications on Applied Electronics
%@ 2394-4714
%V 7
%N 12
%P 25-29
%D 2018
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Now a day’s research has explore in development of prototype devices using different technology. The ECG processing is remained a important research topic as it is useful for the human being directly. Present paper deals with design and implementation of IIR Elliptic digital filter on FPGA for noise reduction in ECG Signal. In this paper filter designed with specifications like order 2, cutoff frequency 100Hz. The simulated results and complete step by step design of the filter is depicted in the paper. The results obtained shows the implementation is advantages considering area, power and Speed.

References
  1. Bahram Rashidi,Bahman Rashi,Majid Pourormazd,“Design andImplementation of LowPower Digital FIR Filter based on low power multipliers and adders on xilinx FPGA” 3rd International Conference on Electronics Computer Technology (ICECT), 2011, Kanyakumari pp 18 – 22.
  2. Vladimir M. Poučki, Andrej Žemva, Miroslav D. Lutovac “Elliptic IIR filter sharpening implemented on FPGA” Digital Signal Processing Vol. 20, Issue 1,January 2010, pp13–22.
  3. Suvadip Roy, L. Srivani, D. Thirugnana Murthy, “Digital Filter Design Using FPGA” International Journal of Engineering and Innovative Technology (IJEIT) Volume 5, Issue 4, October 2015
  4. M.Z. Ikram, Siddiqui N.A, K. A. Meraim, Hia Y.“Design and implementation of IIR filters in STLC7545 analog front-end for voice communication” Proceedings of IEEE Region 10 Annual Conference on Speech and Image Technologies for Computing and Telecommunications., Brisbane, Qld., Australia, vol.1 pp. 65 – 67.
  5. C. Rader, “DSP history—the rise and fall of recursive digital filters,” IEEE Signal Process. Mag., vol. 23, pp. 46–49, Nov. 2006.
  6. B. Gold and C.M. Rader, “Digital filter design techniques in the frequency domain,” Proc. IEEE, vol. 55, no. 2, pp. 149–171, Feb. 1967.
  7. Michael Francis, “Infinite Impulse Response Filter Structures in Xilinx FPGAs” Xilinx WP330 (v1.2) August 10, 2009.
  8. C. Saritha, V. Sukanya, Y. Narasimha Murthy “ECG Signal Analysis Using Wavelet Transforms”, Bulg. J. Phys. 35 (2008) 68–77.
  9. L. Cromwell, F.J. Weibell, E.A. Pfeiffer (2005) Biomedical Instrumentation and Measurements, Prentice Hall of India, New Delhi
  10. Harish V. Dixit, Dr. Vikas Gupta, “IIR filters using Xilinx System Generator for FPGA Implementation”, International Journal of Engineering Research and Applications Vol. 2, Issue 5, September- October 2012, pp.303-307.
  11. Anurag Aggarwal, Astha Satija, Tushar Nagpal, “FIR Filter Designing using Xilinx System Generator”, International Journal of Computer Applications Volume 68– No.11, April 2013.
  12. Kumudini Sahu, Rahul Sinha,” FIR Filter Designing using MATLAB Simulink and Xilinx system Generator” International Research Journal of Engineering and Technology (IRJET) Volume: 02 Issue: 08 Nov-2015.
  13. Gaikwad, S.R., Gawande, G. S. “Design and Implementation of Efficient FIR Filter Structures using Xilinx System Generator” International Journal of scientific research and management (IJSRM) Volume-2,Issue-3,Pages-599-604.
  14. Patel, S.“Design and Implementation of 31-order FIR Low-pass Filter using Modified Distributed Arithmetic based on FPGA” International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering Vol. 2, Issue 10, ISSN: 2320 – 3765.
  15. Ayesha Firdous, Dr.B.Rajan, “A Comparative Study of Pipelining Techniques for Recursive Filter Implemented in FPGA”, International Journal of Scientific & Engineering Research, Volume 5, Issue 4, April-2014 pp.330-333.
  16. Chi-Jui Chou, Satish Mohanakrishnan, Joseph B.Evans,”FPGA Implementation of Digital Filters,”, Proc.ICSPAT’93.
  17. Emmanuel S. Kolawole, Warsame H.Ali, Penrose Cofie, John Fuller, C. Tolliver, Pamela Obiomon, “ Design and Implementation of Low-Pass, High-Pass and Band-Pass Finite Impulse Response (FIR) Filters Using FPGA” Circuits and Systems, 2015, 6, 30-48.
  18. Sushmitha.C, Swathy.R, Veena Devi.S, Esther Jeba Rani.S.A, Nagaraju.N , “Design and Simulation of FIR Filter”, International Journal of Innovative Research in Science, Engineering and Technology,Volume 5, Special Issue 2, March 2016, pp 241-245.
  19. Shahnam Mirzaei, Anup Hosangadi, Ryan Kastner , “FPGA Implementation of High Speed FIR Filters Using Add and Shift Method” International Conference on Computer Design, pp 308-313.
  20. Sweety Kashyap, Mukesh Maheshwari, “Implementation of High Performance FIR Filter Using Low Power Multiplier and Adder” Int. Journal of Engineering Research and Applications Vol. 4, Issue 1( Version 1), January 2014, pp.177-181.
  21. Kaustubh M. Gaikwad, Mahesh S. Chavan “Vedic Mathematics for Digital Signal Processing Operations: A Review” International Journal of Computer Applications (0975 – 8887) Volume 113 – No. 18, March 2015.
  22. Mahesh Chavan, R. A. Agarwala, M.D. Uplane” Application of chebyshev Type II digital filter for noise reduction in ECg Signal” Proceedings of the 5th WSEAS international Conference on Signal Processing, computational Geometry and Artificial Vision”, Malta, Sept.15-17,2005 pp 2-8.
Index Terms

Computer Science
Information Sciences

Keywords

XSG Elliptic Filter noise Removal.

Powered by PhDFocusTM