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Reduction Technique for Power Leakage in Complementary Metal Oxide Semiconductor Circuit using Deep Submicron Technology
| Communications on Applied Electronics |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 7 - Number 19 |
| Year of Publication: 2018 |
| Authors: Anjali Sharma, Jyoti Jain |
10.5120/cae2018652779
|
Anjali Sharma, Jyoti Jain . Reduction Technique for Power Leakage in Complementary Metal Oxide Semiconductor Circuit using Deep Submicron Technology. Communications on Applied Electronics. 7, 19 ( Aug 2018), 16-21. DOI=10.5120/cae2018652779
Abstract
Leakage power reduction has become a major factor in all modern electronic hand held and portable devices due to advancement in the scaling of all Complimentary metal oxide semiconductor devices and circuits. For the reduction of power leakage in the circuit we have used a technique to reduce leakage power at various gates. The approach used here is stack with pass transistor for reduction of leakage power in various gates in the circuit. A parallel combination of NMOS and PMOS transistor is used in parallel for enabling stacking of the transistor for leakage reduction in pull up and pull down network of the transistor. In pull up network NMOS transistor is inserted in parallel to PMOS sacked transistor to maintain Logic level 1. NMOS transistor gets connected to Vdd in pull up Network in sleep mode then pass transistor cut off which achieves a reduction of leakage of 44.63%, 44.63%, 87.02 and 87.44% at 25 Celsius as calculated in two input NAND gate. Also there is a reduction in the Average dynamic power as 15.24%, 15.28%, 35.20%, 31.20% respectively. Area, Delay and Power requirement is satisfied by choosing particular variant of NAND gate. Hence, a trade off is made among these parameters. This technique is also implemented in One bit Full Adder for Low Power leakage design of the circuit.
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