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Design of a Novel Fused Add-Sub Module for IEEE 754-2008 Floating Point Unit in High Speed Applications

Abhyarthana Bisoyi, Aruna Tripathy. Published in Circuits and Systems.

Communications on Applied Electronics
Year of Publication: 2020
Publisher: Foundation of Computer Science (FCS), NY, USA
Authors: Abhyarthana Bisoyi, Aruna Tripathy

Abhyarthana Bisoyi and Aruna Tripathy. Design of a Novel Fused Add-Sub Module for IEEE 754-2008 Floating Point Unit in High Speed Applications. Communications on Applied Electronics 7(33):1-7, February 2020. BibTeX

	author = {Abhyarthana Bisoyi and Aruna Tripathy},
	title = {Design of a Novel Fused Add-Sub Module for IEEE 754-2008 Floating Point Unit in High Speed Applications},
	journal = {Communications on Applied Electronics},
	issue_date = {February 2020},
	volume = {7},
	number = {33},
	month = {Feb},
	year = {2020},
	issn = {2394-4714},
	pages = {1-7},
	numpages = {7},
	url = {},
	doi = {10.5120/cae2020652854},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}


A multiplier block can be implemented either by shift add technique, Booth algorithm or Vedic algorithm, in DSP applications. However, these techniques do not work for a certain class of numbers known as exceptions. They are +infinity, -infinity and Not a Number (NaN). The solution to address these exceptions is a “Fused add-subtract” module. The addition and subtraction modules are fused together to give two outputs giving both addition and subtraction results. The time delay and the number of Look-Up Tables (LUTs) of the existing Fused add-subtract unit have been found to be quite high to meet the present-day requirements of speed. Therefore, a novel algorithm for fused add-subtract has been proposed in this paper. In the floating-point unit (FPU), building blocks of the addition and subtraction are fused together, resulting in reduction of the number of computations as well as the area usage. The existing fused add-sub module is compared with the proposed module in terms of delay and the number of LUTs. The new algorithm is observed to reduce the time delay and area by 12.5% and 18.878% respectively as compared to the conventional one.


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Floating Point Unit, fused add-sub, Multipliers, Time Delay, Functional Area, Digital Circuits, Digital Signal Processing, FPGA