This paper presents a combined architecture of Advanced Encryption Standard-128 encryption and decryption for high speed application. A select line named enc/dec is used to select either of the two operations. If enc/dec is 0, then encryption will take place and if it's 1 then decryption. Pipelining and sub-pipelining is used to enhance the speed of operation. Use of 9 stage sub-pipelining per round unit gives a throughput of 18. 773 Gbps on Xilinx Virtex XCV3200E-8-BG560 device whereas it gives a throughput of 24. 930 Gbps on SPARTAN 3 XC3S4000-5fg676 device.

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AES; Rijndael; pipelining; encryption; decryption