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Reseach Article

Creating a Versatile S-Box for an N-bit AES Algorithm using Reversible Logic

by Rohini S.H., Rajashekar B. Shettar, Supriya K., Rajeshwari M.
Communications on Applied Electronics
Foundation of Computer Science (FCS), NY, USA
Volume 7 - Number 40
Year of Publication: 2025
Authors: Rohini S.H., Rajashekar B. Shettar, Supriya K., Rajeshwari M.
10.5120/ijca2025652906

Rohini S.H., Rajashekar B. Shettar, Supriya K., Rajeshwari M. . Creating a Versatile S-Box for an N-bit AES Algorithm using Reversible Logic. Communications on Applied Electronics. 7, 40 ( Feb 2025), 22-26. DOI=10.5120/ijca2025652906

@article{ 10.5120/ijca2025652906,
author = { Rohini S.H., Rajashekar B. Shettar, Supriya K., Rajeshwari M. },
title = { Creating a Versatile S-Box for an N-bit AES Algorithm using Reversible Logic },
journal = { Communications on Applied Electronics },
issue_date = { Feb 2025 },
volume = { 7 },
number = { 40 },
month = { Feb },
year = { 2025 },
issn = { 2394-4714 },
pages = { 22-26 },
numpages = {9},
url = { https://www.caeaccess.org/archives/volume7/number40/creating-a-versatile-s-box-for-an-n-bit-aes-algorithm-using-reversible-logic/ },
doi = { 10.5120/ijca2025652906 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2025-02-04T00:09:54.080626+05:30
%A Rohini S.H.
%A Rajashekar B. Shettar
%A Supriya K.
%A Rajeshwari M.
%T Creating a Versatile S-Box for an N-bit AES Algorithm using Reversible Logic
%J Communications on Applied Electronics
%@ 2394-4714
%V 7
%N 40
%P 22-26
%D 2025
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In the state of art technology, substantial amount of research on quantum computers is explored. Mathematical problems unsolved by present day computers are well addressed by quantum device, such future computers are capable of breaking existing public key crypto-systems very well. Any cryptographic technique’s strength depends on the key size and secure transmission. To overcome the security issues and attacks by future computers, we propose quantum resistant and generalized approach to AES(Advanced Encryption Standard). AES is the most widely used symmetric key and block cipher cryptographic algorithm, known for its high security, speed, and strength. According to Shannon's theorem, achieving optimal security requires a one-to-one correspondence between each bit of the message and each bit of the key, meaning that the lengths of both the key and the message should be the same. Hence, we proposed an approach , where message size is increased from 128 bits to 192, 256, 512 and 1024 bits and key size is also made same as that of message size. The security of AES algorithm is enhanced by creating dynamic S-Box, as S-Box used in standard AES is static throughout AES encryption. The confusion capability for AES is provided by this S-Box. The S-Box used in standard AES is static throughout the encryption process. In order to make AES more secure, dynamic S-Box is created. This dynamic S-Box is made dependent on message and key. Each time S-Box varies according to message and key. The implementations of AES with message sizes of 192, 256, 512, 1024 and key sizes as that of message size are discussed. Dynamic S-Box is proposed and implemented using reversible logic to mitigate the power dissipation. The proposed scheme is simulated and the analysis of power is carried out using the Genus tool, proving it to be efficient in terms of power, gate usage, garbage, and quantum cost. Testing of dynamic S-Box is done using hamming distance, strict avalanche effect, correlation factor.

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Index Terms

Computer Science
Information Sciences

Keywords

AES S-Box Key Dynamic S-Box